1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a self-aligned contact in a semiconductor device.
2. Description of the Related Art
As the integration level of dynamic random access memory (DRAM) devices increases, the minimum feature size of elements and the space occupied by the elements are reduced. Misalignment may occur during the photo process used to form contact holes. As a result, the insulating layer etching process used to form the contact holes may expose a lower conductive layer, generating a short between the exposed conductive layer and a conductive layer filling a contact hole. In order to solve these problems, a self-aligned contact (referred to below as a "SAC") is suggested. If the minimum feature size of the elements is too small to secure a misalignment margin in the photo process, the SAC process should be used. However, the SAC process has a few problems, as described below.
Referring to FIG. 1, gate lines 14 are grown on a semiconductor substrate in the Y-direction. An active region 10b, which is surrounded by a device isolation region 12, is formed to the X-direction (i.e., perpendicular to the gate lines 14). An interlayer insulating film is formed on the semiconductor substrate and the gate lines 14, and a bar-type photoresist pattern 20 is formed on the interlayer insulating film. Using the photoresist pattern 20 as a mask, the interlayer insulating film is etched.
Referring to FIG. 2A, an active region 10b and an inactive region 12 are shown on a semiconductor substrate 10a. The device isolation region 12 is formed on a gate oxide layer (not shown) over semiconductor substrate 10a. A conductive layer for a gate electrode and an insulating layer for a gate mask are sequentially formed. Using a mask (not shown), the insulating layer is etched to form a gate mask 14b. Using the gate mask 14b, the conductive layer is etched to form a gate electrode 14a. The gate mask may be made of silicon nitride.
Referring to FIG. 2B, a silicon nitride layer 14c and an interlayer insulating film 16 are sequentially formed on an overall surface of the semiconductor substrate 10a including the gate electrode 14a and gate mask 14b. The interlayer insulating film 16 is planarized through a chemical mechanical polishing (CMP) process. The silicon nitride layer 14c serves as an etch-stop layer.
A photoresist layer is patterned on the interlayer insulating film 16, so that a photoresist pattern (not shown) is formed. Using the photoresist pattern as a mask, the interlayer insulating film 16 is etched down to a top surface of the silicon nitride layer 14c in the regions not covered by the photoresist pattern, as shown in FIG. 2C. The silicon nitride layer 14c is anisotropically etched down to a top surface of the active region 10b, so that a silicon nitride layer spacer 14c is formed on both sidewalls of the gate electrode 14a and the gate mask 14b. After formation of the gate electrode 14a and the spacer 14c, an impurity ion is implanted into the active region 10b, so that a source/drain region (not shown) is formed. Then, the photoresist pattern is removed.
Referring to FIG. 2D, a conductive layer (for example, a polysilicon layer) is formed on the overall surface of the semiconductor substrate 10a including the spacers 14c and gate masks 14b, filling the gaps between the gates 14. The conductive layer is then planarized using a CMP process. During this process, the gate mask 14b serves as an etch-stop layer. Thus, a contact plug 18 is formed using the above SAC process.
However, this prior art method may create problems as follows:
(1) In order to expose the semiconductor substrate 10a where the contact plug 18 is formed, the interlayer insulating layer 16 and the nitride layer 14c may be overetched resulting in imperfect formation of the silicon nitride spacer 14c and exposing an edge of the gate electrode 14a. Consequently, a short may occur between the edge of the gate electrode 14a and a pad formed during subsequent processing; PA1 (2) If the gate mask 14b and the silicon nitride layer 14c are made thick enough to accommodate overetching, the space between gates 14 may become too narrow. This narrow space makes filling the space with the interlayer insulating film 16 difficult, resulting in the formation of void regions V, as shown in FIG. 2B. Because these voids are formed in the direction of the word lines of a DRAM device, conductive areas may be electrically connected via the voids during subsequent pad formation, thereby generating undesirable pad-to-pad bridges; and PA1 (3) Because of its small width, misalignment of the bar-type photoresist pattern 20 may cause problems. If the photoresist pattern 20 is misaligned, it may cover part or all of the interlayer insulating film 16 on the active region 10b. Consequently, the contact area between the contact plug 18 to the semiconductor substrate 10a may be reduced, increasing contact resistance. In severe cases, there may be no electrical contact between the contact plug 18 and active region 10b. PA1 (1) A spacer may be imperfectly formed, thus exposing the gate electrode so that a pad-to-gate electrode short is generated. However, this type of pad-to-gate electrode short may be reduced or eliminated in the present invention; PA1 (2) The generation of void regions may be reduced or eliminated without increasing the thickness of the gate mask, thereby reducing or eliminating pad-to-pad bridging in the present invention; and PA1 (3) The photoresist pattern may be formed to secure enough contact area between a pad and an active region in spite of misalignment of the photoresist pattern, thereby reducing or eliminating an increase in contact resistance therebetween.